use ieee.std_logic_1164.all;
entity dchu is
port (
clk : in std_logic;
aclr : in std_logic;
apre : in std_logic;
d : in std_logic;
q :out std_logic
);
end;
architecture ffq of dchu is
signal
q1:std_logic;
begin
process (apre,aclr,clk,q1)
begin
if aclr='1' then
q1<='0';
elsif apre='1'
then q1<='1';
elsif clk'event and clk='1'
then q1<=d;
end if;
end process;
q<=q1; end ffq;
同步清零触发器